課程大綱

課程資訊

課程名稱

積體電路設計
INTEGRATED CIRCUIT DESIGN

開課學期

95-2

授課對象

電機資訊學院電機工程學系

授課教師

吳安宇

課號

EE3020

課程識別碼

901 40500

班次

學分

全/半年

半年

必/選修

選修

上課時間

星期五5,6,7(12:20~15:10)

上課地點

電二106

備註

總人數上限：100人

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課程概述

Outline:

- Chapter 1: Introduction (IC circuits and system designs)
- Chapter 2: Manufacturing Process of CMOS (Appendix: IC Layout)
- Chapter 3: Devices: PMOS and NMOS (Appendix: Circuit Simulation)
- Chapter 4: Wires in modern CMOS circuits (Become Effective in Nano-scale IC design)
- Chapter 5: CMOS inverter (most basic gate)
- Chapter 6: Designing Combinational Logic Gates in CMOS
- Chapter 7: Designing Sequential Logic Circuits
- Chapter 10: Timing Issues in Digital Circuits
- Chapter 11: Designing Arithmetic Building Blocks
- Chapter 12: Designing Memory and Array Structures
- Chapter 8: Implementation Strategies for Digital ICs (VLSI Design Methodology)
- Extra Lecture: Low-Power CMOS Designs

VLSI Lab contents: Use UMC 0.18um Process

Lab0 Setup Working Environment 　
　 1. Use X-window tool to connect to workstation 　
　 2.Use Workstation 　
　　　
Lab1 Hspice Use INVERTER (INV) circuit as an example, including DC & Transition analysis
　 1. Hspice overview
　 2. Circuit simulation by Hspice
　　　
Lab2 Circuit Layout & Verification Use INV circuit for example and 3-input NAND for practice
　 1. Process & layout
　 2. Layout environment & tool
　 3. Verification environment & tool
　　　
Lab3 (I) One-Bit Mirror Adder Design 　
　 1. Practice the Full-custom design flow 　
　 (II) 4-Bit Adder Design 　
　 1. Practice cascading sub-circuits 　
　　　
Lab4 4-bit Accumulator Design Provide the DFF circuit for the design
　 1. Practice the flip-flop design
　 2. Learn and analyze the relation of the setup time, hold time, critical path, and etc in the circuit design
　

課程目標

What can you learn from this course?
1. Basic understanding of CMOS device and its physical properties.
2. Basic CMOS processing technology and its relationship with Layout
3. Basic CMOS logic, circuits and layout
4. Estimation of CMOS performance in terms of area, power, and speed.
5. Basic VLSI subsystems such as Adder, Subtractor, RAM, and ROM.
6. VLSI CAD tools (Layout tools, SPICE) and CAD-based VLSI Design Homework
7. Digital IC design concept and design flow.

What are NOT covered in this course?
1. Analog/Mixed-mode IC designs (You can take Prof. C. K. Wang or Prof. Shen-Iuan Liu’s course)
2. VLSI system designs such as CPU, Digital Filters, DSP blocks
3. Computer-aided Digital IC Design Flow (Synthesis and Place-and-Route tools)
4. An exhausting large-scale VLSI final project (covered by another course- VLSI Design Laboratory for undergraduate students)
5. Verilog/VHDL Hardware Description Language (HDL) – will be covered by “Digital System Design” course.

課程要求

Grading method:
1. Participation 2% (about 四次點名). This part can be recovered if your final grade is above 90.
2. One mid-term Exam 26%
3. Final Exam 30% (cover all teaching materials)
4. VLSI Design Labs (around 5 VLSI computer labs and homework): 36%
5. Quiz (6%)
6. No copy of homeworks!!! It is considered as cheating (Ethics in University)

預期每週課後學習時數

Office Hours

每週五 10:00~12:00

指定閱讀

參考書目

Reference: Advanced reading for ASIC and VHDL/Verilog:

1. “Verilog硬體描述語言數位電路設計實務”, 作者: 鄭信源, 儒林圖書有限公, 網址: www.scholars.com.tw, 2000年 (good for new users).
2. “Advanced Digital Design with the Verilog HDL,” by Michael D. Ciletti, Prentice Hall, 2003 (新月圖書) – with Verilog Simulator.
3. “Verilog HDL: A Guide to Digital Design and Synthesis,” 2nd ed., by Samir Palnitkar, SunSoft, 2003 (全華代理)
4. “Verilog Styles for Synthesis of Digital Systems,” by David R. Smith and Paul D. Franzon, Prentice Hall, 2000 (全華代理)
5. Verilog 硬體描述語言 (Verilog HDL), 原著: Samir Palnitkar, 原出版社: Prentice Hall, 編譯: 黃英叡, 黃稚存, 張銓淵, 江文啟, 全華科技圖書, 88年.
6.

評量方式
(僅供參考)

No.	項目	百分比	說明
1.	Participation	2%	about 四次點名
2.	One mid-term Exam	26%
3.	Final Exam	30%	Cover all teaching materials.
4.	Quiz	6%
5.	VLSI Design Labs	36%	Around 5 VLSI computer labs and homework

課程進度

週次

日期

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